PINCFG=00, PCSCFG=0, NOSTALL=0, AUTOPCS=0, PCSPOL=0, MATCFG=000, MASTER=0, OUTCFG=0, SAMPLE=0
Configuration Register 1
| MASTER | Master Mode 0 (0): Slave mode. 1 (1): Master mode. |
| SAMPLE | Sample Point 0 (0): Input data sampled on SCK edge. 1 (1): Input data sampled on delayed SCK edge. |
| AUTOPCS | Automatic PCS 0 (0): Automatic PCS generation disabled. 1 (1): Automatic PCS generation enabled. |
| NOSTALL | No Stall 0 (0): Transfers will stall when transmit FIFO is empty or receive FIFO is full. 1 (1): Transfers will not stall, allowing transmit FIFO underrun or receive FIFO overrun to occur. |
| PCSPOL | Peripheral Chip Select Polarity 0 (0): The PCSx is active low. 1 (1): The PCSx is active high. |
| MATCFG | Match Configuration 0 (000): Match disabled. 2 (010): Match enabled (1st data word equals MATCH0 OR MATCH1). 3 (011): Match enabled (any data word equals MATCH0 OR MATCH1). 4 (100): Match enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1). 5 (101): Match enabled (any data word equals MATCH0 AND next data word equals MATCH1) 6 (110): Match enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1) 7 (111): Match enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1). |
| PINCFG | Pin Configuration 0 (00): SIN is used for input data and SOUT for output data. 1 (01): SIN is used for both input and output data. 2 (10): SOUT is used for both input and output data. 3 (11): SOUT is used for input data and SIN for output data. |
| OUTCFG | Output Config 0 (0): Output data retains last value when chip select is negated. 1 (1): Output data is tristated when chip select is negated. |
| PCSCFG | Peripheral Chip Select Configuration 0 (0): PCS[3:2] are enabled. 1 (1): PCS[3:2] are disabled. |